1. Field
Exemplary embodiments of the present invention relate to an integrated circuit chip and a memory device, and more particularly, to a technology of testing whether each pad (pin) of an integrated circuit chip has been electrically connected to a substrate (board).
2. Description of the Related Art
When an integrated circuit chip such as a memory device is attached to a board, a test is performed to check a bonding state regarding whether bonding of a package has been normally made and pins have been normally connected to the board. The conventional art uses a scheme for testing a bonding state of a board and pins using a test scheme called a boundary scan test. However, since this scheme performs a test by shifting a test pattern, significant time is required.
In a recent memory device, a connectivity test scheme of simultaneously applying signals to a plurality of pads of a chip and testing an electrical connection state of the pads in a parallel manner has been proposed. In this regard, a chip design that stably supports a connectivity test of new scheme is required.